1. Field of the Invention
The present invention relates to a semiconductor memory device which can be reused by skipping defective memory cells even if they are found therein.
2. Description of the Related Art
One type of conventional nonvolatile semiconductor memory device where data can be rewritten by the user is an erasable programmable read-only memory (EPROM) using cell transistors of a floating gate avalanche injection metal oxide semiconductor (FAMOS) structure and the like. In the EPROM, data can be written using a write device called a programmer (writer) and all data written in its memory cells can be erased at the same time by ultraviolet irradiation. The EPROM realizes a one transistor/one cell structure which reduces the area of one memory cell, allowing a larger amount of memory cells to be integrated in one chip, resulting in a large memory capacity and a low bit unit cost. However, the EPROM needs to use a ceramic package with expensive quartz glass for ultraviolet irradiation at the erase operation, preventing the chip unit cost from becoming even lower. Moreover, at the data write operation, a special write device is exclusively used. Chips must be mounted on a system via a socket to which chips are detachably attached. This attachment/detachment of chips at the write operation is troublesome, and the packaging cost increases.
One type of conventional electrically rewritable nonvolatile semiconductor memory device is an electrical EPROM (EEPROM) using cell transistors having a floating gate of a floating gate tunnel oxide (FLOTOX) structure which utilizes Fowler-Nordheim (FN) tunnel current and the like. The EEPROM is advantageous in that electrical data writing and erasure are possible while chips are kept mounted on a system. However, a selective transistor is required for each memory cell, increasing the area of one memory cell one and a half times to twice that of the EPROM. This increases the bit unit cost, which is disadvantageous for obtaining a large capacity.
A flash memory has conventionally been developed as a nonvolatile semiconductor memory device having the advantages of the EPROM and the EEPROM. As shown in FIG. 22, a memory cell of such a flash memory includes a cell transistor of a MOSFET (metal oxide semiconductor field effect transistor) structure and a floating gate 92 with an insulating gate oxide film residing underneath a control gate 91 of the cell transistor, as disclosed in U.S. Pat. No. 5,249,158, for example. This memory cell realizes the one transistor/one cell structure with no selective transistor. Thus, the bit unit cost is as low as that of the EPROM which is advantageous for obtaining a large capacity. Moreover, since electrical data writing and erasure are possible, an inexpensive plastic package can be used, eliminating the troublesome attachment/detachment of chips. Incidentally, data erasure is conducted for every chip unit or for every erase block unit when a chip is divided into a plurality of erase blocks.
When data is written in the cell transistor of the above flash memory, the control gate 91 is applied with a high voltage of about 12 V, a source 93 is grounded (0 V), and a drain 94 is applied with a voltage of about 7 V, simultaneously. Then, a large current flows between the drain 94 and the source 93, allowing high-energy hot electrons generated near the drain junction to be injected into the floating gate 92 and accumulated therein. Thus, the cell transistor with data written therein has a high threshold voltage with respect to the control gate 91, whereby data "1", for example, is stored. This method of injecting hot electrons into the floating gate 92 needs a large current of about 1 mA supplied to each cell transistor at the write operation. To overcome this problem, a modified type of flash memory has been developed where the current required at the write operation is reduced by injecting electrons by use of an FN tunnel current, as in the normal EEPROM.
When data is erased, the source 93 is applied with a high voltage of about 12 V and the control gate 91 is grounded simultaneously. Then, a high electric field is generated between the floating gate 92 and the source 93, allowing the electrons accumulated in the floating gate 92 to be drawn off therefrom via the thin gate oxide film by a tunnel current. This reduces the threshold voltage of the cell transistor, erasing the stored data. Since no selective transistor is included in the cell transistor of the flash memory, when an excessive amount of electrons are drawn off from the floating gate 92 (excessive erasure), the threshold voltage of the cell transistor becomes negative, allowing a leak current to flow. As a result, access to cell transistors on the same bit line is blocked, causing a decisive defect. At the data erase operation, therefore, measures for preventing the excessive erasure are required.
In the above erasing method, since the source 93 is applied with a high voltage as described above, the withstand voltage at the source junction must be kept high. This makes it difficult to minimize the size of the source electrode side. Moreover, some of the hot holes generated near the source junction are trapped in the gate oxide film, lowering the reliability of the cell transistor. To overcome these drawbacks, a modified erasing method has been developed where the source 93 is applied with a source voltage V.sub.CC (normally, about 5 V) and the control gate 91 is applied with a negative voltage of about -10 V, thus drawing off electrons accumulated in the floating gate 92 (negative gate erasing method). According to the negative gate erasing method, since the voltage applied to the source 93 is low, the withstand voltage at the source junction can be reduced, which allows the gate length of the cell transistor to be shortened. Moreover, in the former erasing method where a high voltage is applied to the source 93, the total tunnel current flowing between bands in the entire chip at the erase operation reaches several mA. A normal booster circuit with a small current supply capability is not enough to supply the high voltage, necessitating an external power source to supply a high voltage V.sub.PP for erasure. According to the negative gate erasing method, however, only a source voltage V.sub.CC (5 V or 3 V) is supplied to the source 93. Thus, it is comparatively easy to realize a flash memory having a single power source supplying only the source voltage V.sub.CC.
When data is read, the source 93 is grounded (0 V), the drain 94 is applied with a low voltage of about 1 V, and the control gate 91 is applied with the source voltage V.sub.CC (normally, about 5 V) simultaneously. Then, when electrons have not been accumulated in the floating gate 92, the cell transistor is activated due to the low threshold voltage, allowing a drain current to flow between the drain 94 and the source 93. When data has been written and electrons have been accumulated in the floating gate 92, the cell transistor is kept disabled due to the high threshold voltage, allowing little drain current to flow between the drain 94 and the source 93. By detecting the level of the drain current, data "0" or "1" stored in the cell transistor can be read. The voltage to be applied to the drain 94 is as low as 1 V at the read operation so as to prevent parasitic weak write (soft write) from occurring due to application of a high voltage.
In the above cell transistor of the flash memory, writing is conducted on the drain junction side, while erasure is conducted on the source junction side. It is desirable therefore to optimize the profiles of these junctions in the device design according to the respective operations. More specifically, the drain junction side and the source junction side are made asymmetrical using a field concentration type profile for the drain junction to increase the write efficiency and a field relaxing type profile for the source junction to allow a high voltage to be applied at erasure.
Unlike RAMs (random access memories) and the like, the flash memory has many operation states such as block erase, chip batch erase, and read of state register, in addition to data write and read. Accordingly, in order to designate these operation states by combinations of control signals such as a chip enable signal CE bar and a write enable signal WE bar which are supplied externally, additional control signals other than conventional signals used in the EPROM and EEPROM must be defined and respective input terminals for these additional control signals are required. This makes the device less convenient. Practical flash memories therefore mainly employ a command method as disclosed in U.S. Pat. No. 5,053,990, where combinations of data and addresses, not combinations of control signals, are used as commands to designate the respective operation states. In such flash memories, types of commands input externally are identified by a command state machine (CSM) and a write state machine (WSM, an automatic erase/write control circuit) executes operations according to the commands.
Besides the EEPROM and the flash memory using a floating gate as described above, nonvolatile semiconductor memory devices using a ferroelectric thin film are also used. Two such nonvolatile semiconductor memory devices, one using the ferroelectric thin film as a ferroelectric disposed in a capacitor of a DRAM (dynamic RAM) and one using the ferroelectric thin film as a gate oxide film of a cell transistor, have been developed.
The above conventional nonvolatile semiconductor memory devices are fabricated in an extremely precise semiconductor process. Therefore, some percentage of memory cells may inevitably be found defective. However, if a semiconductor chip including a defective memory cell is discarded, the production yield is decreased. In DRAMs and SRAMs (static RAMs), a redundancy circuitry has been adopted where redundant memory cells are provided, in addition to main memory cells. When defective memory cells are detected, they can be replaced with redundant memory cells by laser trimming. With this method, the yield of the nonvolatile semiconductor memory device improves. Using a redundancy circuitry in the nonvolatile semiconductor memory device has also been proposed (for example, U.S. Pat. No. 5,267,213 and No. 5,379,249), where a content addressable memory (CAM) circuit having electrically writable nonvolatile memory cells is used in place of a fuse for switching by laser trimming and the like.
Referring to FIG. 23, the CAM circuit includes nonvolatile memory circuits in a quantity corresponding to a required amount of bits. Each nonvolatile memory circuit includes a pair of serial circuits each composed of a P-channel MOSFET 95, an N-channel MOSFET 96, and a cell transistor 97 of a flash memory and connected between a power source V.sub.CC and the ground. Each gate of the MOSFETs 95 is connected to each source of the opposing MOSFETs 95. Each gate of the MOSFETs 96 is applied with a bias voltage of a predetermined level, for example, about 2 V. As used herein, the terminal of a transistor from which a current flows when the transistor is in an ON state is referred to as the source, while the terminal of the transistor into which a current flows when the transistor is in the ON state is referred to as the drain, though these may be reversed.
One-bit CAM data can be stored in the cell transistors 97 in a nonvolatile manner as will now be described. In this CAM circuit, each control gate of the cell transistors 97 is applied with a high voltage V.sub.PP of 12 V, and each drain of the cell transistors 97 is applied with a complementary program voltage supplied from a CAM program circuit 98 so that one of the drains of the cell transistors 97 becomes 7 V (high level) and the other drain of the cell transistors 97 becomes 0 V (low level).
Reading of data from the cell transistors will be described. The CAM program circuit 98 applies a low voltage of 1 V or so to each drain of the cell transistors 97. Each control gate of the cell transistors 97 is applied with the source voltage V.sub.CC. The source potential of one of the MOSFETs 95 becomes equal to either the source voltage V.sub.CC or the ground voltage depending on the memory content. This voltage can be read as 1-bit CAM data via an inverter 99. A switch circuit is controlled based on the thus-read CAM data to realize the switching between the main memory cell and the redundant memory cell.
In the nonvolatile semiconductor memory device using the above-described CAM circuit, if a memory having a memory capacity of 4M bits is fabricated, main memory cells in a quantity corresponding to 4M bits and redundant memory cells in an appropriate quantity are formed. When any defective memory cell is found at a test prior to packaging, CAM data corresponding to this defective memory cell is set in the CAM circuit, thereby replacing the defective memory cell with a redundant memory cell. Accordingly, after the replacement of the memory cell, the memory capacity of 4M bits is retained, and thus the resultant product can be considered the same as others where no defective memory cell is found.
An invention of switching the bit configuration and operation mode of a nonvolatile semiconductor memory device based on data stored in a nonvolatile memory cell, as in the CAM circuit, has been proposed (Japanese Laid-Open Patent Publication No. 6-131879).
An invention of changing the function of a read-only semiconductor memory device by use of a mask pattern used when data is written in a mask ROM has also been proposed (Japanese Laid-Open Patent Publication No. 2-63162).
The above conventional nonvolatile semiconductor device using the CAM circuit has a problem that will now be described. When no defective memory cell is found, the memory capacity for the redundant memory cells is wasted, increasing the production cost due to the enlarged circuit size for the redundant memory cells. Such redundancy circuitry is useful for early production lots where the defective rate is high. As the production is gradually stabilized or the production technique is improved, lowering the defective rate, the wasteful portion of the memory increases, which may become a factor of preventing cost reduction.
The inventions disclosed in Japanese Laid-Open Patent Publication No. 6-131879 and No. 2-63162 only relate to changes of the functions such as the bit configuration and operation mode of a semiconductor memory device, not responding to defective memory cells. The latter invention is only applicable to a mask ROM.